Since I am moving forward to big data/data mining directions, I would like to summarize my experience on ASIC verification and provide the resources which may be helpful to you guys.
Here’s my conclusion for Verilog interview questions if you want to be an ASIC designer.
My conclusion of SystemVerilog interview questions if you want to be an ASIC verification Engineer.
3. UVM interview questions
The best one for now is just reviewing this website
4. Other resources
4. 1 Websites
1) SystemVerilog for Verification: A Guide to Learning the Test-bench Language Features
2) The UVM Primer: A Step-by-Step Introduction to the Universal Verification Methodology
A decent entry level UVM book with source code provided. You can build and learn a complete simple UVM test-bench.